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AMD Bulldozer processor architecture

September 19th, 2010 Leave a comment Go to comments

Bulldozer is the codename of the next generation of the CPU architecture that will take on the Intel’s next generation (Sandy Bridge ?) processor architecture. After a lot of delays ( this was not completely unexpected, given the complexity in the ground up design proves and AMD’s history of delaying the product launch) the bulldozer based processor are finally expected to arrive in 2011.

AMD’s bulldozer architecture consists of modules. Each module has two cores. So, a bulldozer based processor with single module will have two cores. A dual module bulldozer core will have 4 cores.

AMD plans to release processors with 8 modules with a total of 16 cores. The bulldozer based processors will have 8MB to 16MB of L3 cache which will be shared by all the modules on the same silicon die. The bulldozer architecture will have integrated DDR3 memory controller and there will be support for upto DDR3-1866. The memory controller will have high Level of Parallelism for efficient memory transfers.

The memory controller will be Quad Channel DDR3 for Desktops. It will have support for the Registered DDR3 for server and workstation market.

The bulldozer architecture is a 32nm SOI process implemented with High-K Metal Gate (HKMG). It will have the support for Intel’s Advanced Vector Extensions (AVX).However, the Advanced Vector Extensions will require applications to be recompiled if they want to take advantage of 256-bit floating point.

Connection to the chipset will be supported with next generation of the HyperTransport version 3.1. The HyperTransport 3.1 will work at 3.20 GHz, which means, working with both the rising and falling edge of clock gives effective transfer rate of 6.4 Giga Transfers per second/s. The HyperTransport is a bidirectional bus. There will be 16 bit lane in each of the upwards and downwards direction (need to confirm).

In contrary to the Intel’s Hyperthreading, AMD’s architecture uses real, physical cores to handle multiple threads. The Intel’s hy HyperThreading also execute two threads on a single core but the process is slightly different than that of the AMD’s.

The problem with intel’s Hyperthreading, as AMD explains – “is that it exploits gaps in the execution pipeline in order to get that second thread running”. If you are inefficiently executing applications, you do have have gaps in the pipeline and you get your second thread exploit the gap to get executing. If your software and the execution process is efficient, you do net get opportunity to take advantage and there is really little gain, if any by way of hyperthreading.

AMD’s bulldozer will have real physical cores. In heavily optimized systems, the real physical core is the way to go, since there is little inefficiency left that can be exploited.

The bulldozer architecture will have two dedicated integer cores. Each of these integer cores will consist of 2 Arithmetic Logic Unit 2 AGU. These two together can execute 4 independent arithmetic or memory operations per clock cycle per core.

The integer core has duplicating integer schedulers. The execution pipelines offers dedicated hardware significantly increasing performance in multi-threaded integer applications.

It will be interesting to see how Intel reacts to the thread from bulldozer. Apparently, the only issue that is seen from AMD’s end is the delay. The verification and validation process do take time. By the time we are keeping our fingers crossed. While we definitely know that bulldozer will launch in 2011 – the real question is – when in 2011.

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