Archive for the ‘hardware’ Category

Difference Between a Combinational and Sequential Circuit

April 26th, 2011 4 comments

Question – What is the Difference between a Combinational and a Sequential Circuit.

Answer – In a Combinational Circuit, the present output depends only upon the present input. Past input or the sequences of the inputs is immaterial. There is no memory element in the combinationation circuit. If you are implementing a purely combinational circuit on a CPLD or a FPGA, you will typically not need any “clock”, used to step through the “states” or the memory elements. The pure combinational circuit can be composed entirely with the help of logic gates ( AND, OR, NOT, XOR, XNOR etc). Karnaugh mapping is used to minimize the number of gates required to implement a Combinatorial Circuit.

The Sequential Circuit has memory element and the output depends nor only upon the present input, but also upon the pas input or the “state” of the system. or the “memory” of the system. A sequential circuit has flip flops to store the “state” or the registers of the system. A sequential circuit, generally has a clock used to step through the different states of the systems. Typically at each (rising) edge of the clock, the sequential circuit advances to the next state.

Example of a Combinational Circuit

– It is required to check if 4 digit number is has odd parity or an even parity. The system will give out 1 if the parity of the 4 digits is even and will give 0 otherwise. This circuit, can, for example be used to check the error in transmission.

The circuit can be implemented using Boolean Logic and using gates. It can more easily be implemented using Verilog or VHDL Hardware Description Language.

Example of a Sequential Circuit

A system takes a sequence of byte data on its 8 input pin system. The system should give an output, whenever it detects a particular sequence, for example a sequence of 0x01, 0x07, 0x11 and 0x02. Under all other circumstances it will give 0 output.

– The solution to this problem will require a clock which will be used input the values. The clock will also be used to store the intermediate values as the system goes through different states. This will require use of flip flops for implementation.

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Interview Question in Verilog / FPGA #1

April 24th, 2011 3 comments

Here are some of the popular Interview questions for Verilog. It may make sense to know about them even if you are experienced designer, as, this will help you present your knowledge as an academician.

Q1. What is the difference between a blocking and non blocking statement in Verilog ? Explain with an Example.

A. The Assignment Statements in the Verilog can be blocking or non blocking. If we wish that the value of a register to change sequentially during a clock edge, we should use the blocking assignment. The blocking and non blocking assignment operators are depicted using = and <= assignment operators. The difference between them is best understood with an example.

// difference between a blocking and non-blocking assignment

module blocking_assignment ;
reg [0:7] X, Y;

begin: init1
X = 5;
#1 X = X + 1; // At this stage X will assigned a value of 6
Y = X + 1; // Now X has a value 7 and Y has value 7
$display(“Blocking: X= %b Y= %b”, X, Y ); // This will display

A = 5;
#1 A <= A + 1;
B <= A + 1; // The non blocking assignment means that B is assigned value of 6
#1 $display(“Non-blocking: A= %b B= %b”, A, B );

produces the following output:
Blocking: A= 00000110 B= 00000111
Non-blocking: A= 00000110 B= 00000101

In the non blocking statement the value of the variable at the beginning of the current time is taken and the value is assigned to the registers.
In general, combinatorial logic use blocking assignments and the sequential logic uses the non blocking statement.

Q2. What does #5 in the following code do ?

a = 1; c = 0;
b = #5 a + c;

The statement b = #5 a+c evaluates the value of a+c at time t =0 and then wait for 5 time units and then assigns the value to b.

Q3. What does the following code do in Verilog

`timescale 2ns / 5ps

The time scale defines the time unit in multiple of after which an event can occur. It is defined as
`timescale time_unit/time_precision

Delays in timescale are are multiples of time_unit. The precision is defined by time_precision.
In the example

`timescale 2ns/5ps
#1.55 a = b;
‘a’ gets ‘b’ after 3.1 ns because 2ns*1.55 = 3.10 ns. Notice that here 5 ps is meaningless as the precision is not required. However, in the code
`timescale 10ns/0.1ns
#1.055 a = b;
‘a’ gets ‘b’ after 10.6 ns because 1ns*1.055ns = 10.55ns = 10.6ns rounded to the nearest 10 ps

Q4. What is purpose of a constraint file what is its extension?

The UCF file is an ASCII file specifying constraints on the logical design. You create this file and enter your constraints in the file with a text editor. You can also use the Xilinx Constraints Editor to create constraints within a UCF(extension) file. These constraints affect how the logical design is implemented in the target device. You can use the file to override constraints specified during design entry.

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April 23rd, 2011 No comments

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Verilog is a Hardware Description Language (HDL), used to design a digital circuits. It is similar to other software programming languages ( Like C, Java) but, is specifically tuned for writing programs for the cominational and sequential digital circuits. It is also use in the implementation of state diagram and verification of digital circuits. Verilog has also been extended to cover Analog and mixed signal circuits.

Verilog has led to tremendous improvement in the productivity in the design of Electronics System. Prior to the development of the Hardware Description Languages ( HDL), the designers used to draw the Schematics, which was then translated into the technology for the fabrication of chips. As the sizes of the circuit start growing, it was no more possible to maintain a huge amount of circuit using Schematics. The Schematics provides a pictorial view of the digital or the Analog System being implemented.

In many ways, Verilog is similar to the software programming language like C/C++. It has similar control statements like if/else statement, for and while loop, and case statement. Verilog uses begin and end in place of curly brackets { and } to demarcate the start and end of the procedural blocks.

A Verilog design consist of modules. A simple design will have only one single module, but a complex design consists of a large number of hierarchical modules which may contain dependencies between them.The top module may call few modules which, in turn may call more modules in a complex hierarchy. By breaking a design in a large number of modules it is possible for many persons to work on different parts of a design. A module has input, output and inout ( bidirectional) ports.

Withing a module we may have a large number of combinational and sequential blocks. One of the important aspect of the Verilog programming construct is the concurrent execution of the the individual blocks. While the statements within a block are placed between a begin and end block. While the statements within the block are executed sequentially, the block themselves execute concurrently.

Synthesis of Verilog Code

Once the Verilog code has been written and checked for the syntax accuracy, it is generally tested for desired functionality using test bench. In a test bench, all possible variations of the stimuli is given and the programmer look for the desired output. The testing of verilog code is an extensive process often taking more time than the design itself. Glitches ( even a single error) in the Verilog can be expensive, especially, if it is a ASIC design.

Once the Code has been compiled, and extensively tested, it is synthesized either for an FPGA or an ASIC. The Synthesis software is an additional technology dependent software implemented by technology companies. The Synthesis software transforms the RTL code of Verilog into a net list consisting of primary logic primitives and interconnection between them. The primitives consists of AND, OR, NOT gates, buffers, flip flops, Look up Tables etc.

Once the Synthesis netlist is generated it can be used to generate a bitstream file that can be used by FPGA. An ASIC requires further processing , including generation of circuit fabrication blueprint to fabricate ASIC.

Here are Some common Questions about Verilog and its History.

Q. When was Verilog Started ?

A. Verilog was started in 1984 by Dr. Prabhu Goel and Phil Moorby ( Source – at Gateway Design Automation, which was later on purchased by Cadence in 1990.

Q. When Verilog was under Cadence, why did it make the language public.
A. The VHDL was getting popular around 1995, which led Cadence to make the language public for Standardization. Verilog was subsequently transferred to publlic domain under Open Verilog International (OVI). It was later on submitted to IEEE and became IEEE 1364-1995 standard.

Q. What about Verilog 2001 ? What are the major changes in Verilog 2001 ?

A. The Verilog 2001 is a major upgrade to the Verilog 1995. IEEE released it as a new standard IEEE 1364-2001. Here are some examples  of the new features include
– Explicit support for 2’s complement, signed nets and variable.
– The File I/O operation has been improved using a large number of new system-tasks.
– Comma used in sensitive list – You can now use always @( a,b,c) in place of always @( a or b or c).
– You can use a * to describe a sensitivity list on the right hand side of a assignment statement
Example 2001 – always @(*) z = a + b + c ;
Example 1995 – always @(a or b or c) z = a + b + c ;
– 2001 introduced new data types
* <<< : Shift left, to be used on signed data type ( note << is a signed shift) * >>> : shift right, to be used on signed data type
* ** : exponential power operator.

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Intel Core i5-460M vs. core i5-520M – comparison and difference

February 25th, 2011 No comments

Today, we have come up with a comparison between two popular processors. Those are Intel Core i5 Mobile i5-460M and Intel Core i5-520M. Let us see each and every aspect in detail with both processors.

Here, i5-460M is credited with two cores and four threads with a clock speed of 2.53 GHz and max Turbo frequency is 2.8GHz. Whereas, i5-520M is credited with similar cores and threads but clocked at 2.4GHz and Max turbo frequency is 2.933 GHz. It is indicating that the i5-520M gained upper hand with Turbo frequency and i5-460M gained attention with clock speed.

If we see into the Intel Smart Cache capacity, both are credited with 3MB. Here Bus/Core ratio is differed a little bit as i5-460M is with 19 and i5-520M is with 18. Similarly both got equal DMI as 2.5GT/s and both got 64-bit instruction set. There is a significant difference with Embedded Options availability. I5-520 got this facility and i5-460M is lacking this facility.

Both processor are with similar TDP rating and Lithography with 35W and 32nm. Similarly, both processors got equal memory specifications without any differences. Surprisingly, both processors are carrying the similar Graphics specifications without any change. The expansion options availability is also same with both processors.

When advanced technologies are verified with both processors, the i5-520M is credited with more facilities. This i5-520M additionally got Intel Virtualization Technology for Directed I/O (VT-d), Intel Trusted Execution technology, and AES New Instructions. The common advanced technologies between both processors are Intel Turbo Boost technology, Intel Hyper-Threading Technology, Intel Virtualization Technology (VT-x), Intel 64, Idle States, Enhanced Intel Speedstep Technology, Thermal Monitoring Technologies, Intel Fast Memory Access, Intel Flex Memory Access and Execute Disable Bit.


The package specifications of the each processor are completely matching well with each other without any differences. Here, i5-520M was released in Q1-2010 and i5-460M released in Q3-2010.

With this background it is really difficult to say, which of these two processors are better. The Table below lists out the side by side comparison, showing some benchmark results as well.

Table : A comparison Table of Core i5-460M vs. core i5-520M


SL No. Core i5-460M Core i5-520M
Clock Frequency 2.53 GHz 2.40 GHz
Turbo Freq 2.80 GHz 2.93 GHz
Embedded Option No Yes
AES instructions No Yes
VT-d No Yes
Trusted Execution Technology No Yes
Super Pi 2M Benchmark (Lower is better) 37 seconds 38 Seconds
3D Mark 06 Benchmark ( Higher is better) 2925 2730
SiSoft Sandra Dhrystone 38500 34500
Windows 7 Experience Index 6.9 6.8


From the Table it is hard to make derive any definite conclusion in favor of one processor. The only reason the Core i5-520M will be preferable is when you plan to use some of its features, including the AES instructions sets, Trusted Execution and the higher turbo frequency. Otherwise the performance of the two processors are comparable.

Comparison sourced from below links:


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Colibri – Tegra 2 OEM module from Toradex

February 20th, 2011 No comments

Toradex has been one of the foremost companies, that has come up with Tegra 2 based OEM module. Nicknamed Colibri Tegra 2, the module comes as an SODIMM card and has the Nvidia’s Tegra 2 CPU. The Tegra 2 CPU is based upon dual Cortex A9 running at 1 GHz.

The integrated graphics from the procesor leads to great graphics performance. You may end up getting great graphics performance, even when the processor’s processing power is not used.

The COlibri has an HDMI interface, that can be used to display the High Definition contents on the televisions or other devices that can take in the HDMI input. The colibri Tegra 2 has USB 2.0, I2C, SPI and GPIO busses to connect a large number of peripherals.

Toradex has a decent migration path where existing sockets can utilize this module. The only extra is the HDMI which comes a separate connector. To take full advantage of the capabilitied of the Colibri Tegra 2, you may like to have a fresh carrier board design.

Colibri Tegra 2 OEM Module Pros

– Small form factor
– Great processor, terrific performance, especially graphics
– HDMI support
– Fits in existing carrier designs.

Colibri Tegra 2 OEM Module Cons

– It comes wit only 256 MB of RAM

Here are the list of the Features in the Colibri Tegra 2 module as detailed by Toradex.

– NVIDIA Tegra 2 Cortex-A9 – 2 Core
-32KB Instruction and 32KB Data L1 cache
– 1 MB shared L2 Cache
-VFPv3 Floating Point Support
– 256 MB DDR2 RAM and 1Gbyte NAND FLASH
– 16/32 Bit Data Bus
– LCD RGB (1680 x 1050)
-Full HD 1080p HDMI
– Analog Video 1600×1200
– 4 as well as 5 wire Touch Screen
– Audio
-CMOS camera inteface
–¬† I2C, 4 SPI, 5 UART
–¬† 2 SDCard support
– 10 GPIOs
– USB 2.0 high speed hosts and device
– 10/100 Mbit Ethernet
– One-Wire, Keypad, 4x PWM, S/PDIF

Colibri Tegra 2 OEM Module has pretty much everything that you need in an embedded environment. YOu may however, need you own additional circuit to support your applications. Some of the things that you may need include a USB 2.0 Hub,

Here are the includes external chips, besides the RAM and the NAND Flash in the Colibri Tegra 2 OEM Module

1. Asix AX88772B Ethernet chip for ethernet controller
2. Wolfson WM9715L for Audio

The SODIMM module is 200 pins. The Colibri modules fit into a regular 2.5V (DDR1) SODIMM200 memory socket. A choice of SODIMM200 socket manufacturers is given belowThere is another 24 pin connector for the HDMI and video output.

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