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D Flip Flop, HDL Verilog Code and Circuit

April 27th, 2011

A D Flip Flop is a basic storate element. The block Diagram below shows the structure of a basic D Flip Flop

The Output q of the Flip Flop , typically, Changes only at the rising edge of the clock. If at any moment of time the output of q is at logic 1, it will stay at 1 until the next rising edge of the clock. So the D-Flip flop “stores” the value. If at the next rising edge of the clock if the input d is 0, the output becomes 0 ( and 1 if the input D is 1). The Table below show the truth table for a basic d Flip Flop.

Clk Output q*
0 q
1 q
Rising Edge d

In many cases it may be desirable to have a Flip Flop attain a desired and “defined” initial value ( typically a 0 value). This is done with another Reset input to the Flip Flop. When a reset signal is applied to a Flip Flop, its output is set to 0. The reset signal can be asynchronous with respect to the clock signal or may take action only on the rising or the falling edge of clock. In the latter case it is called D-Flip Flop with Synchronous reset.

The Verilog RTL code for a D Flip Flop is as follows.

module dff(

input wire clk, d,
output reg q
);
always @(posedge clk)
q <= d ;
endmodule

A D-Flip Flop with Asynchronous Reset.

The Table shows a D-Flip FLop with an Asynchronous Reset

[table id=1 alternating_row_colors= true /]

The Verilog code for a D-Flip Flop with asynchronous reset is shown below

module dff(

input wire clk, d,reset,
output reg q
);
always @(posedge clk, posedge reset)
if ( reset)
q <= 1'b0;
else
q <= d ;
endmodule

Timing Parameters for a D-Flip Flop

There are three timing parameters of a D Flip Flop that you need to be aware of, if you are designing a real high speed system where timing does matter.

Tcq = Clock to output delay. It is the time its takes for the data to propagate through the D-Flip Flop
Tc = The maximum delay of the next state combinational logic
Tsetup = Setup Time constraint of the closed loop.

The minimum clock period for the closed loop is obtained by adding the three clock periods

Tmin >= Tcq + Tc + Tsetup

The clock period must be greater than the sum of these three clock periods. If you happen to violated this equation, you need to reduce the frequency of the clock till we satisfy this equation. The maximum frequency of operation is given by

fmax = 1/ (Tmin) = 1/(Tcq + Tc + Tsetup)

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