More recent processors from Intel including the core i3, i5 and i7 processors come with integrated memory controller. A processor having integrated memory controller communicates with the memory directly. This is a departure from the designs of the earlier Intel processors, including the core 2, dual core and the Pentium 4 processors, in which the processor did not have memory controller and they did not communicate with the memory directly. Instead, the processors communicated with a chipset, more popularly called North Bridge. The North Bridge, in turn used to communicate to the memory controller.
A block diagram, taken from the intel website, showing the earlier architecture withe memory controller built in the North Bridge ( Intel officially calls it Memory Controller Hub) is shown in the diagram below.
There was certain advantage in moving the memory controller to the North Bridge, in place of the integrating it into the processor itself. Way back in early 1990s, the direction of the memory technology was not clear. There were several competing technologies ( SDRAM, DDR, other ?) each with its own pros and cons. If processor designer choose one memory technology, they would stuck with that technology and there was no way they could choose other memory technology even if they wished to.
The architecture of the processor system, therefore, decided to move the memory controller to the North Bridge. If, at any point, any one wanted to try a different memory system, they could change the North Bridge. The Processor stays same. This approach provided flexibility. However moving the memory controller to the north bridge came with its own set of problems. The processor had to communicate to the north bridge first, which in turn communicated to the memory. This increase the memory latency and reduced the overall system performance.
By the mid 1990s the DDR bus started becoming gaining more acceptance among memory menufacturers. AMD reasilised this and took the lead in taking the risk of moving the memory controller on the processor. By early 2000, AMD’s opteron series of the server processor, started rolling out. These were based upon the DDR integrated memory controller. Intel still continued with its older approach. Intel overcome the memory issue by increasing the amount of the cache in the processors.
Soon Intel realized that DDR2 and DDR3 are the stable technologies, it followed the AMD suite. With its core i3 , i5 and i7 processors, intel had the DDR3 integrated memory controller. A typical block diagram of the architecture with integrated memory controller, taken from Intel is shown in the block diagram below.
Notice that the Memory (in green on the left of the CPU ) is connected directly to the processor. The newer integrated memory controller improved the performance of the core i3, core i5 and core i7 processor significantly.