Interview Question in Verilog / FPGA #1
Here are some of the popular Interview questions for Verilog. It may make sense to know about them even if you are experienced designer, as, this will help you present your knowledge as an academician.
Q1. What is the difference between a blocking and non blocking statement in Verilog ? Explain with an Example.
A. The Assignment Statements in the Verilog can be blocking or non blocking. If we wish that the value of a register to change sequentially during a clock edge, we should use the blocking assignment. The blocking and non blocking assignment operators are depicted using = and <= assignment operators. The difference between them is best understood with an example.
// difference between a blocking and non-blocking assignment
module blocking_assignment ;
reg [0:7] X, Y;
X = 5;
#1 X = X + 1; // At this stage X will assigned a value of 6
Y = X + 1; // Now X has a value 7 and Y has value 7
$display(“Blocking: X= %b Y= %b”, X, Y ); // This will display
A = 5;
#1 A <= A + 1;
B <= A + 1; // The non blocking assignment means that B is assigned value of 6
#1 $display(“Non-blocking: A= %b B= %b”, A, B );
produces the following output:
Blocking: A= 00000110 B= 00000111
Non-blocking: A= 00000110 B= 00000101
In the non blocking statement the value of the variable at the beginning of the current time is taken and the value is assigned to the registers.
In general, combinatorial logic use blocking assignments and the sequential logic uses the non blocking statement.
Q2. What does #5 in the following code do ?
a = 1; c = 0;
b = #5 a + c;
The statement b = #5 a+c evaluates the value of a+c at time t =0 and then wait for 5 time units and then assigns the value to b.
Q3. What does the following code do in Verilog
`timescale 2ns / 5ps
The time scale defines the time unit in multiple of after which an event can occur. It is defined as
Delays in timescale are are multiples of time_unit. The precision is defined by time_precision.
In the example
#1.55 a = b;
‘a’ gets ‘b’ after 3.1 ns because 2ns*1.55 = 3.10 ns. Notice that here 5 ps is meaningless as the precision is not required. However, in the code
#1.055 a = b;
‘a’ gets ‘b’ after 10.6 ns because 1ns*1.055ns = 10.55ns = 10.6ns rounded to the nearest 10 ps
Q4. What is purpose of a constraint file what is its extension?
The UCF file is an ASCII file specifying constraints on the logical design. You create this file and enter your constraints in the file with a text editor. You can also use the Xilinx Constraints Editor to create constraints within a UCF(extension) file. These constraints affect how the logical design is implemented in the target device. You can use the file to override constraints specified during design entry.