StateCAD for State Diagrams in Xilinx ISE
Xilinx ISE free version ( as of 13.1) does not automatically include the StateCAD program, a utility that allows a user to draw a State Diagram in graphical manner.
With StateCAD you can create state machines and the tool automatically translate it into HDL code. With StateCAD you can develop the initial state machine, a Logic Wizard to create data flow structures. Further, you can use an Optimization Wizard which will maximize the performance for a target device.
Once you enter a design free State diagram, StateCAD can translate it into synthesizable Verilog COde ( wor VHDKL if you want. The HDL code then can be used in the Foundation Series ISE project.
Additionally the StateBench automatically creates test benches from the StateCAD designs. Here are the steps required to create new state diagram using State Bench
1. Using a new Source in project, Create the state diagram.( You will require StateCAD to be pre-installed – not included with the default installation of Xilinx ISE 13.1)
2. Create a new State Diagram using StateCAD.
3. Verify for the State Diagram to be error free. Try using StateBench, for testing functionality.
4. StateCAD creates a synthesizable HDL file from the verified state diagram.
5. You may like to add state diagram source files to your project. The State diagram files have extension .dia. You may like to Add the StateCAD-generated HDL file in the project.
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The Xilinx website lists out the procedure for using the State Cat that can be found at http://www.xilinx.com/itp/3_1i/data/fise/xug/chap07/xug07002.htm. However, this procedure call for some CD called ALLSTAR CD, that has the StateCAD. Unfortunately we do not find any reference for StateCAD’s free version anywhere in the online