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Verilog Case Statement


Verilog Case Statement

Syntactically, a verilog case statement includes all the code between keywords “case” and “endcase”. A typical case statement looks as follows

case (case_expresssion)

case_item1 : statement1;
case_item2 : statement2;
case_item3 : statement3;
case_item4 : statement4;
default : statement5;

endcase

The case statement can also be represented using a set of if else statement. The above case statement can be written using if then statement as follows

if (case_expression === case_item1) statement1;
else if (case_expression === case_item2) statement2;
else if (case_expression === case_item3) statement3;
else if (case_expression === case_item4) statement4;
else statement5;

Here is an actual example showing the use of the Verilog case statement

module mux (x,y,z,p,sel,y);
input x,y,z,p;
input [1:0] sel;
output y;

reg y;

always @ (x or y or z or p or sel)
case (sel)
0 : y = x;
1 : y = y;
2 : y = z;
3 : y = p;
default : $display("Error in SEL");
endcase

endmodule

In this example, depending upon the vale of the sel, the output y gets assigned to one of the inputs x, y, z or p.

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