Home > Uncategorized > Verilog Full Case and Parallel Case

Verilog Full Case and Parallel Case


In this article we will explore Verilog full case and and parallel case, two variants of the verilog case statement. The verilog full case and parallel case should be used cautiously as these may lead to issues where synthesis simualtion may show up different from the behavioral simulation.

You may like to know about verilog case statement, before taking up this article.

Verilog Full Case

If all possible case-expression binary patterns are matched to a case item or to a case default the case statement is a Full case statement.

If a case statement is such that there exists at least one a binary case expression that does not match any of the defined case items, then the case statement is not “full.”

HDL Simulation Vs Syntesis Full Case

From HDL Simulation perspective a Verilog Full case is one in which the binary as well as non binary case-expression is matched to a case item or to a case default. The non binary case-expression include ‘z’ and ‘x’.

From Synthesis perspective a Verilog Full case is one in which the binary case-expression is matched to a case item or to a case default.

It is not essential that Verilog be a Synthesis full or a HDL simulation full. A simple way to make a Verilog case statement to be a full case statement is to add a case default.

Verilog Full Case example

The following is an example of a verilog full case for a multiplexer

module mux3c (y, a, b, c, sel);
output y;
input [1:0] sel;
input a, b, c;
reg y;
always @(a or b or c or sel)
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
default: y = 1'b0;
endcase

The following example show a non full case multiplexer

module mux3a (y, a, b, c, sel);
output y;
input [1:0] sel;
input a, b, c;
reg y;
always @(a or b or c or sel)
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
endcase
endmodule

Notice that there is no case statement corresponding to the case expression 2’b11.

A Verilog Parallel Case Statement

A verilog case statement is a Parallel case statement if a case expression matches to one and only one case item. If a case expression matches to more than one case item then the case statement is not a Verilog parallel case statement.

An Example of a Case statement that is not parallel

module priority (in2, in1, in0, irq);
output in2, in1, in0;
input [2:0] irq;
reg int2, int1, int0;
always @(irq) begin
{in2, in1, in0} = 3'b0;
casez (irq)
3'b1??: in2 = 1'b1;
3'b?1?: in1 = 1'b1;
3'b??1: in0 = 1'b1;
endcase
end
endmodule

Notice that the following case expressions do not translate to unique case item

110
111
101
100

As an example in case when irq has value 110, it matches to the following two case items

3’b1??: in2 = 1’b1;
3’b?1?: in1 = 1’b1;

In real simulation it the case item that occurs earlier will be executed. In other words it will act as a priority encoder.

Categories: Uncategorized Tags:
  1. No comments yet.