Verilog Value Set
Verilog Value Set by Starred Reviews
Besides 0 and 1 a Verilog set can have have Value z and x.
x – represents an unknown logic value
z – The z value represents a high impedance vale.
The logic values x and z are usually part of the simulation process and are monitored for completeness of the verification process. These are also compared against the post synthesis simulation process.
The effect of the high impedance value when present on an imput is same at the value x. However, there are some exceptions, for example, the MOS primitives can pas the z value.
Except for the event type, all the data types in the Verilog HDL store all the four values.It is possible to set the individual bits of a vector to an any of the 4 values.
The Verilog also allows a strength information to be assigned to a net variable in addition to the basic value.