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Verilog

April 23rd, 2011 Leave a comment Go to comments

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Verilog is a Hardware Description Language (HDL), used to design a digital circuits. It is similar to other software programming languages ( Like C, Java) but, is specifically tuned for writing programs for the cominational and sequential digital circuits. It is also use in the implementation of state diagram and verification of digital circuits. Verilog has also been extended to cover Analog and mixed signal circuits.

Verilog has led to tremendous improvement in the productivity in the design of Electronics System. Prior to the development of the Hardware Description Languages ( HDL), the designers used to draw the Schematics, which was then translated into the technology for the fabrication of chips. As the sizes of the circuit start growing, it was no more possible to maintain a huge amount of circuit using Schematics. The Schematics provides a pictorial view of the digital or the Analog System being implemented.

In many ways, Verilog is similar to the software programming language like C/C++. It has similar control statements like if/else statement, for and while loop, and case statement. Verilog uses begin and end in place of curly brackets { and } to demarcate the start and end of the procedural blocks.

A Verilog design consist of modules. A simple design will have only one single module, but a complex design consists of a large number of hierarchical modules which may contain dependencies between them.The top module may call few modules which, in turn may call more modules in a complex hierarchy. By breaking a design in a large number of modules it is possible for many persons to work on different parts of a design. A module has input, output and inout ( bidirectional) ports.

Withing a module we may have a large number of combinational and sequential blocks. One of the important aspect of the Verilog programming construct is the concurrent execution of the the individual blocks. While the statements within a block are placed between a begin and end block. While the statements within the block are executed sequentially, the block themselves execute concurrently.

Synthesis of Verilog Code

Once the Verilog code has been written and checked for the syntax accuracy, it is generally tested for desired functionality using test bench. In a test bench, all possible variations of the stimuli is given and the programmer look for the desired output. The testing of verilog code is an extensive process often taking more time than the design itself. Glitches ( even a single error) in the Verilog can be expensive, especially, if it is a ASIC design.

Once the Code has been compiled, and extensively tested, it is synthesized either for an FPGA or an ASIC. The Synthesis software is an additional technology dependent software implemented by technology companies. The Synthesis software transforms the RTL code of Verilog into a net list consisting of primary logic primitives and interconnection between them. The primitives consists of AND, OR, NOT gates, buffers, flip flops, Look up Tables etc.

Once the Synthesis netlist is generated it can be used to generate a bitstream file that can be used by FPGA. An ASIC requires further processing , including generation of circuit fabrication blueprint to fabricate ASIC.

Here are Some common Questions about Verilog and its History.

Q. When was Verilog Started ?

A. Verilog was started in 1984 by Dr. Prabhu Goel and Phil Moorby ( Source – http://www.uta.edu/oit/cs/software/altera/quartus-ii-4/index.php) at Gateway Design Automation, which was later on purchased by Cadence in 1990.

Q. When Verilog was under Cadence, why did it make the language public.
A. The VHDL was getting popular around 1995, which led Cadence to make the language public for Standardization. Verilog was subsequently transferred to publlic domain under Open Verilog International (OVI). It was later on submitted to IEEE and became IEEE 1364-1995 standard.

Q. What about Verilog 2001 ? What are the major changes in Verilog 2001 ?

A. The Verilog 2001 is a major upgrade to the Verilog 1995. IEEE released it as a new standard IEEE 1364-2001. Here are some examples  of the new features include
– Explicit support for 2’s complement, signed nets and variable.
– The File I/O operation has been improved using a large number of new system-tasks.
– Comma used in sensitive list – You can now use always @( a,b,c) in place of always @( a or b or c).
– You can use a * to describe a sensitivity list on the right hand side of a assignment statement
Example 2001 – always @(*) z = a + b + c ;
Example 1995 – always @(a or b or c) z = a + b + c ;
– 2001 introduced new data types
* <<< : Shift left, to be used on signed data type ( note << is a signed shift) * >>> : shift right, to be used on signed data type
* ** : exponential power operator.

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