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What is new in the Intel Sandy Bridge Architecture

January 15th, 2011 Leave a comment Go to comments


If you follow the processors evolution you are probably familiar with the Sandy Bridge processors that have started appearing in notebooks and desktops shortly after the CES 2011 shows. Here are the main summary of new features in the Sandy Bridge Processor.

– The Memory Controller and the graphics controller now reside on the same die as the two cores. This is unlike the earlier architecture in which the memory controller and the graphics were on one core while the two cores of the CPU were on the other die. Also in the earlier Nehalem architecture the two processor cores were built with 32 nm process while the memory controller was built with 45 nm technology. In the Sandy Bridge we have a unified die built with 32 nm technology.

– There is a change in the L3 cache architecture – that intel now calls Last Level Cache ( or LLC). The graphics can now share thi cache in addition to the processor cores. The graphics, now do not need to go to the RAM to fetch the data. It improves the graphics performance.

– Sandy Bridge processors have new AVX (Advanced Vector Extensions) instruction set. The AVX instruction sets are the extensions of the SSE instructions set. The AVX adds 12 new instructions. The increases the size of the XMM registers ( XMM registers are kind of registers used by SSE and other instructions) from 128 bits to 256 bits. AVX uses a big register to store several small data and processes all data in one signle instruction).


– Sandy Bridge processors have improved Turbo Boost. Intel realized that the Heat Sink and the processor still stay cool, it extended the time for which the processor could operate in the Turbo mode. Intel allowed the processors to operate beyond the TDP rating, further improving its performance.

The Sandy Bridge processors have ring architecture. A component inside the CPU, a core, a cache, a graphics controller and System Agent ( comprising of Display, Memory Controller, PCI Express and DMI) talk in a ring fashion.  If there is a four core CPU, it can access data in any other CPU using the ring communication. The Sandy Bridge has new decoded microinstruction cache. The microinstruction cache can store 1,536 microinstructions occupying less than 6 kB that is called L0 cache by Intel. The idea is obvious. This helps if the program is running in a loopp where it will not have to decode the instruction, every time it enters the loop. This instruction will be already decoded by the L0 cache and ready for execution.

– The L1 consists of 32 KB instruction and 32 KB data Cache. We do not have any change from Nehalem architecture.

– The L2 cache is now called mid level cache – and now consists of 256 KB per core.

– Sandy Bridge allows two related instructions to be joined.

– The memory controller has been redesigned and it now supports memories up to DDR3-1333
– Has Integrated PCI Express controller that can give one 16 bit lane of two 8 bit lanes. This stays unchanged from the previous Nehalem architecture.

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